//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
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//-----------------------------------------------------------------------------
//
// Project    : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File       : pcie3_7x_0_pcie_tlp_tph_tbl_7vx.v
// Version    : 4.1
//----------------------------------------------------------------------------//
// Project      : Virtex-7 FPGA Gen3 Integrated Block for PCI Express         //
// Filename     : pcie3_7x_0_pcie_tlp_tph_tbl_7vx.v                                      //
// Description  : Implements the TLP TPH Processing Hints Table for the       //
//                Virtex-7 FPGA Gen3 Integrated Block for PCI Express         //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
//  pcie_tlp_tph_tbl_7vx.v                                                    //
//----------------------------------------------------------------------------//

`timescale 1ps/1ps

module pcie3_7x_0_pcie_tlp_tph_tbl_7vx #
(
  parameter TCQ =  100
) (
  input         user_clk,                       // User Clock
  input         reset_n,                        // Warm, Hot Reset, active low

  input   [4:0] cfg_tph_stt_address_i,          // Address
  input   [2:0] cfg_tph_function_num_i,         // Function #
  input  [31:0] cfg_tph_stt_write_data_i,	      // Write Data
  input         cfg_tph_stt_write_enable_i,	    // Write Data Enable
  input   [3:0] cfg_tph_stt_write_byte_valid_i, // WBE
  output [31:0] cfg_tph_stt_read_data_o,        // Read Data
  input         cfg_tph_stt_read_enable_i,      // Read Data Enable
  output        cfg_tph_stt_read_data_valid_o,	// Read Data Valid

  input   [4:0] user_tph_stt_address_i,         // Address
  input   [2:0] user_tph_function_num_i,        // Function #
  input         user_tph_stt_read_enable_i,     // Read Enable
  output [31:0] user_tph_stt_read_data_o,       // Read Data
  output        user_tph_stt_read_data_valid_o  // Read Data Valid

);



  // Local Registers

  reg                 reg_cfg_tph_stt_read_data_valid_o;
  reg                 reg_user_tph_stt_read_data_valid_o;
  reg [7:0]           reg_count;
  reg                 reg_state = 1'b0; // on cold reset
  reg                 reg_next_state = 1'b0; // on cold reset
  reg                 reg_web;
  reg                 reg_cfg_tph_stt_read_enable_i;
  reg                 reg_user_tph_stt_read_enable_i;

  // Local Wires

  wire                N0, N1;
  wire  [3:0]         wea;
  wire                web;
  wire  [7:0]         addra, addrb;
  wire [31:0]         dina;
  wire [31:0]         dinb;
  wire  [7:0]         count_w;
  wire                ram_scrub_in_process_w;
  wire                state_w;
  wire                next_state_w;
  wire [31:0]         douta;
  wire [31:0]         doutb;

  // cfg_tph_stt_read_data_valid_o generation
  always @ (posedge user_clk or negedge reset_n) begin

    if (!reset_n) begin
      reg_cfg_tph_stt_read_data_valid_o   <= #TCQ 1'b0;
      reg_cfg_tph_stt_read_enable_i       <= #TCQ 1'b0;
    end else begin
      if (cfg_tph_stt_read_enable_i && reg_cfg_tph_stt_read_enable_i &&
          !reg_cfg_tph_stt_read_data_valid_o && !ram_scrub_in_process_w) begin
        reg_cfg_tph_stt_read_data_valid_o <= #TCQ 1'b1;
      end else begin
        reg_cfg_tph_stt_read_data_valid_o <= #TCQ 1'b0;
      end
      reg_cfg_tph_stt_read_enable_i       <= #TCQ cfg_tph_stt_read_enable_i;
    end
  end

  // user_tph_stt_read_data_valid_o generation
  always @ (posedge user_clk or negedge reset_n) begin

    if (!reset_n) begin
      reg_user_tph_stt_read_data_valid_o    <= #TCQ 1'b0;
      reg_user_tph_stt_read_enable_i       <= #TCQ 1'b0;
    end else begin
      if (user_tph_stt_read_enable_i && reg_user_tph_stt_read_enable_i &&
          !reg_user_tph_stt_read_data_valid_o && !ram_scrub_in_process_w) begin
        reg_user_tph_stt_read_data_valid_o <= #TCQ 1'b1;
      end else begin
        reg_user_tph_stt_read_data_valid_o <= #TCQ 1'b0;
      end
      reg_user_tph_stt_read_enable_i       <= #TCQ user_tph_stt_read_enable_i;
    end
  end

  // RAM scrub

  always @ (posedge user_clk) begin

    reg_state <= #(TCQ) next_state_w;

    if (state_w) begin
      reg_count <= #(TCQ) count_w + 1'b1;
    end else begin
      reg_count <= #(TCQ) 8'b0;
    end
  end

  always @ ( * ) begin

    case(state_w)

      1'b0 :
      begin
        if (!reset_n) begin
          reg_next_state = 1'b1;
        end else begin
          reg_next_state = 1'b0;
        end
      end

      1'b1 :
      begin
        if (count_w == 8'hFF) begin
          reg_next_state = 1'b0;
        end else begin
          reg_next_state = 1'b1;
        end
      end
    endcase
  end

  RAMB36E1 #(
    .DOA_REG ( 1 ),
    .DOB_REG ( 0 ),
    .EN_ECC_READ ( "FALSE" ),
    .EN_ECC_WRITE ( "FALSE" ),
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    .INIT_A ( 36'h000000000 ),
    .INIT_B ( 36'h000000000 ),
    .INIT_FILE ( "NONE" ),
    .RAM_EXTENSION_A ( "NONE" ),
    .RAM_EXTENSION_B ( "NONE" ),
    .RAM_MODE ( "TDP" ),
    .RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ),
    .READ_WIDTH_A ( 36 ),
    .READ_WIDTH_B ( 36 ),
    .RSTREG_PRIORITY_A ( "REGCE" ),
    .RSTREG_PRIORITY_B ( "REGCE" ),
    .SIM_COLLISION_CHECK ( "GENERATE_X_ONLY" ),
    .SIM_DEVICE ( "7SERIES" ),
    .SRVAL_A ( 36'h000000000 ),
    .SRVAL_B ( 36'h000000000 ),
    .WRITE_MODE_A ( "WRITE_FIRST" ),
    .WRITE_MODE_B ( "WRITE_FIRST" ),
    .WRITE_WIDTH_A ( 36 ),
    .WRITE_WIDTH_B ( 36 ))
  u_ram  (
    .CASCADEINA(N1),
    .CASCADEINB(N1),
    .CASCADEOUTA () ,
    .CASCADEOUTB () ,
    .CLKARDCLK(user_clk),
    .CLKBWRCLK(user_clk),
    .DBITERR ( ) ,
    .ENARDEN(N0),
    .ENBWREN(N0),
    .INJECTDBITERR(N1),
    .INJECTSBITERR(N1),
    .REGCEAREGCE(N0),
    .REGCEB(N1),
    .RSTRAMARSTRAM(N1),
    .RSTRAMB(N1),
    .RSTREGARSTREG(N1),
    .RSTREGB(N1),
    .SBITERR ( ) ,
    .ADDRARDADDR({N0, N1, N1, addra[7:0], N1, N1, N1, N1, N1}),
    .ADDRBWRADDR({N0, N1, N1, addrb[7:0], N1, N1, N1, N1, N1}),
    .DIADI({dina[31:0]}),
    .DIBDI({dinb[31:0]}),
    .DIPADIP({N1, N1, N1, N1}),
    .DIPBDIP({N1, N1, N1, N1}),
    .DOADO({douta[31:0]}),
    .DOBDO({doutb[31:0]}),
    .DOPADOP(),
    .DOPBDOP(),
    .ECCPARITY(),
    .RDADDRECC(),
    .WEA(wea[3:0]),
    .WEBWE({N1, N1, N1, N1, web, web, web, web})
  );

  assign addra                          = {cfg_tph_function_num_i, cfg_tph_stt_address_i};
  assign dina                           = cfg_tph_stt_write_data_i;
  assign wea[3]                         = cfg_tph_stt_write_enable_i && cfg_tph_stt_write_byte_valid_i[3];
  assign wea[2]                         = cfg_tph_stt_write_enable_i && cfg_tph_stt_write_byte_valid_i[2];
  assign wea[1]                         = cfg_tph_stt_write_enable_i && cfg_tph_stt_write_byte_valid_i[1];
  assign wea[0]                         = cfg_tph_stt_write_enable_i && cfg_tph_stt_write_byte_valid_i[0];
  assign cfg_tph_stt_read_data_o        = douta;
  assign cfg_tph_stt_read_data_valid_o  = reg_cfg_tph_stt_read_data_valid_o;
  assign N0                             = 1'b1;
  assign N1                             = 1'b0;
  assign ram_scrub_in_process_w         = state_w;
  assign count_w                        = reg_count;
  assign state_w                        = reg_state;
  assign next_state_w                   = reg_next_state;
  assign dinb                           = 32'b0;
  assign web                            = reg_next_state;
  assign user_tph_stt_read_data_o       = doutb;
  assign user_tph_stt_read_data_valid_o = reg_user_tph_stt_read_data_valid_o;
  assign addrb                          = ram_scrub_in_process_w ? count_w : {user_tph_function_num_i, user_tph_stt_address_i};

endmodule // pcie_tlp_tph_tbl_7vx
